1. Field of the Invention
The present invention relates to integrated circuit memory devices, and to sense circuitry in such memory devices.
2. Description of Related Art
Integrated circuit memory devices are becoming smaller and faster. One limitation on the size and speed of memory devices arises from circuitry used for precharging and biasing bit lines in preparation for sensing data from the array. Typical structures used for these purposes are illustrated in U.S. Pat. No. 6,219,290, entitled MEMORY CELL SENSE AMPLIFIER, invented by Chang et al.; U.S. Pat. No. 6,498,751, entitled FAST SENSE AMPLIFIER FOR NONVOLATILE MEMORIES, invented by Ordonez, et al.; and U.S. Pat. No. 6,392,447, entitled SENSE AMPLIFIER WITH IMPROVED SENSITIVITY, invented by Rai et al.
Prior U.S. Pat. No. 7,082,061, entitled MEMORY ARRAY WITH LOW POWER BIT LINE PRECHARGE, invented by Chou et al., is incorporated by reference for a discussion of prior art biasing structures. As explained in U.S. Pat. No. 7,082,061, a basic biasing structure used in prior art memory devices comprises a clamp transistor and a load transistor coupled with each bit line. The clamp transistors can comprise cascode transistors having gates coupled to the output of respective feedback inverters. The inputs to the feedback inverters are coupled to the sources of the clamp transistors and to the data line conductors. A dynamic feedback circuit is thus provided that sets up equilibrium condition, with a small current through the load transistor. The voltage at the sense node settles at the target level, and the bit line is ready for sensing. After the interval allowing the voltage at the sense node to settle at the target level, the memory cell is accessed for sensing by applying a word line potential to the gate of the memory cell. This approach requires feedback inverters for each bit line.
In an alternative embodiment known in the prior art, the dynamic feedback inverters are replaced with a static bias voltage VBIAS. The circuit operates in a manner similar to that described above, without the dynamic feedback. As the voltage VBL on the bit line reaches a level that is about a threshold voltage drop across the clamp transistor below the bias voltage VBIAS, the clamp transistor begins to turn off and reduce current flow. The dynamic balance is achieved with the voltage at the sense node settling on a target value. At this point, the precharge step is completed, and the bit line is ready for sensing. This can save layout area. However, it relies on the use of an extra bit line and requires extra bias voltages for the bias voltage regulator. Also, in order to implement low power bit line pre-charge, a higher bias level is applied first, followed by a lower bias level when the voltage of the dummy bit line is near the target voltage. However, the higher then lower bias method can only drive a relatively small number of bit lines being coupled to sense amplifiers at the same time, due for example to charge coupling from the data lines to the bias voltage regulator during the precharge operation.
While these prior art techniques have been applied for memory devices successfully, as memory access speeds increase, component sizes decrease, and more complicated and more highly parallel sensing structures are deployed, the requirement of complex biasing structures on every bit line is becoming a limiting factor on size and cost of integrated circuit memories. Also, as power supply voltages drop and operating speeds increase, overshoot during precharge intervals can reduce the margin for sensing data values in the memory arrays. It is therefore desirable to provide sensing systems that occupy less space on an integrated circuit, operate faster and consume less power.